1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to a configuration for achieving reduction of current consumption as well as high-speed operation of a semiconductor integrated circuit device including a logic gate constituted of a CMOS transistor.
2. Description of the Background Art
In the field of semiconductors, enhancement of integration and reduction of supply voltage are being promoted nowadays.
Since MOS transistors constituting an internal circuit have threshold voltage, the threshold voltage should be made smaller in order to secure a high-speed operation. However, a problem of a dramatic increase in the leakage current arises if the threshold voltage is decreased.
One scheme for solving this problem is a hierarchical power supply system. The hierarchical power supply system employed in a conventional semiconductor integrated circuit device will be described using FIG. 67.
In FIG. 67, a plurality of stages of CMOS inverters X1, X2, X3 . . . connected in cascade are shown as forming one example of an internal circuit.
CMOS inverters X1, X2 and X3 each include a PMOS transistor and an NMOS transistor. A main supply line L1, a sub-supply line L2, a main ground line L3 and a sub-ground line L4 for applying an operation supply voltage are arranged for inverters X1-X3.
A switching transistor T1 is placed between main supply line L1 and sub-supply line L2. Between main ground line L3 and sub-ground line L4, a switching transistor T2 is arranged.
Switching transistor T1 is brought to a conducting state in response to a hierarchical power supply control signal/xcfx86c to electrically connect main supply line L1 and sub-supply line L2.
Switching transistor T2 is brought to the conducting state in response to a hierarchical power supply control signal xcfx86c to electrically connect main ground line L3 and sub-ground line L4.
One operation supply node (a node receiving a higher potential) of inverters at the odd number stages X1, . . . each is connected to sub-supply line L2, and the other operation supply node (a node receiving a lower potential) is connected to main ground line L3.
One operation supply node (a node receiving a higher potential) of inverters at the even number stages X2, . . . each is connected to main supply line L1, and the other operation supply node (a node receiving a lower potential) is connected to sub-supply line L4.
Supply potential is applied to main supply line L1. Ground potential is applied to main ground line L3. Voltage of main supply line L1 is referred to as voltage Vcc, voltage of sub-supply line L2 is referred to as voltage SubVcc, voltage of main ground line L3 is referred to as voltage Vss, and voltage of sub-ground line L4 is referred to as voltage SubVss.
Referring to FIGS. 68 and 69, an operation of the conventional hierarchical power supply system shown in FIG. 67 is hereinafter described.
FIG. 68 illustrates a timing chart showing variation of supply potential in the conventional hierarchical power supply system shown in FIG. 67, and FIG. 69 is provided for describing voltage conditions of respective inverters X1, . . . in a standby cycle.
As shown in FIG. 69, inverters X1, . . . each include a PMOS transistor P1 and an NMOS transistor N1.
An input signal IN which is brought to an H level and an L level respectively in the standby cycle and an activate cycle is input to the internal circuit illustrated in FIG. 69. In the standby cycle, control signal xcfx86c is set at the L level. Accordingly, switching transistors T1 and T2 are in OFF state in the standby cycle. In the active cycle, control signal xcfx86c is set at the H level.
Upon transition from the active cycle to the standby cycle (at time t0 and t2 of FIG. 68), voltage SubVcc of sub-supply line L2 gradually decreases from the voltage Vcc level of main supply line L1 due to the load capacitor. On the other hand, voltage SubVss of sub-ground line L4 gradually changes to a higher level from voltage (ground supply voltage) Vss of main ground line L3 due to the load capacitor.
Upon transition from the standby cycle to the active cycle (at time t1 of FIG. 68), control signal xcfx86c attains the H level. Accordingly, switching transistors T1 and T2 are brought to ON state. Voltage SubVcc of sub-supply line L2 is charged to the voltage Vcc level of main supply line L1. Voltage SubVss of sub-ground line L4 approaches to the voltage Vss level of main ground line L3.
Referring to FIG. 69, in the standby cycle, inverter X2 receives a signal of ground supply voltage Vss which is an inverted one of input signal IN. Accordingly, in inverter X2, PMOS transistor P1 attains ON state, and a connection node between PMOS transistor P1 and NMOS transistor N1 is set at voltage Vcc level of main supply line L1. Since NMOS transistor N1 receives voltage SubVcc of sub-ground line L4 higher than ground supply voltage Vss, the gate voltage becomes smaller than the source voltage. The leakage current in inverter X2 is thus restricted.
Inverter X3 receives a signal of voltage Vcc of main supply line L1. Accordingly, NMOS transistor N1 is brought to ON state, and a connection node between PMOS transistor P1 and NMOS transistor N1 is set at voltage Vss of main ground line L3. Since PMOS transistor P1 receives voltage SubVcc of sub-supply line L2 lower than voltage Vcc of main supply line L1, the gate voltage becomes higher than the source voltage. Accordingly, the leakage current in inverter X3 is restricted.
However, in the conventional hierarchical power supply system, as shown in FIG. 68, at the instant of transition from the standby cycle to the active cycle, switching transistors T1 and T2 are brought into ON state to cause a sudden voltage change of sub-supply line L2 and sub-ground line L4 (referred to as voltage drop).
Further, when switching transistor T1 and T2 attain ON state, the junction capacitance thereof causes voltage SubVcc of sub-supply line L2 to become a level slightly lower than voltage Vcc of main supply line L1 and causes voltage SubVss of sub-ground line L4 to keep a level slightly higher than voltage Vss of main ground line L3.
If the internal circuit operates in this state, a problem arises that an operation feature satisfying a desired condition cannot be obtained and it takes time to define an output from the internal circuit.
In addition, current consumption of a semiconductor integrated circuit device should be effectively decreased according to an operation timing.
The present invention provides a semiconductor integrated circuit device that can operate with low current consumption and at a high-speed.
The invention further provides a semiconductor integrated circuit device that can operate with low current consumption and at a high-speed according to an operation mode.
The present invention further provides a semiconductor integrated circuit device that can monitor the leakage current to adjust current consumption using the result of the monitoring.
A semiconductor integrated circuit device according to one aspect of the present invention includes a main supply line, a sub-supply line, a coupling circuit for electrically coupling the main supply line and the sub-supply line in an active cycle and for electrically uncoupling the main supply line and the sub-supply line in a standby cycle, a logic circuit having a first logic gate operating with voltage on the main supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and having a second logic gate operating with voltage on the sub-supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and a voltage control circuit for controlling voltage on the main supply line to apply to the logic circuit a prescribed operation supply voltage required for ensuring the operation of the logic circuit in the active cycle.
It is therefore a principal advantage in the above aspect of the present invention to be able to reduce the leakage current in the standby cycle by employing the hierarchical power supply system to control supply voltage applied to the logic circuit. An operation speed of the logic in the active cycle can be prevented from being decreased by securing an operation supply voltage in the active cycle. Further, generation of the voltage drop can be restricted by controlling voltage on each supply line.
In particular, the leakage current in the standby cycle can be reduced and an operation supply voltage in the active cycle can be secured by adjusting voltage on a supply line that applies a higher operation supply potential.
In particular, the leakage current in the standby cycle can be decreased and an operation supply voltage in the active cycle can be secured by adjusting voltage on a supply line that applies a lower operation supply potential.
In particular, the leakage current in the standby cycle can be reduced and an operation supply voltage in the active cycle can be secured by adjusting voltage on supply lines that apply a higher operation supply potential and a lower operation supply potential respectively.
In particular, current consumption of the entire circuit can be reduced by independently controlling voltage on a supply line in the standby cycle and that in the active cycle.
In particular, at least one switching transistor is provided for short-circuiting supply lines. Resistance of the supply lines can thus be decreased.
In particular, at least one circuit for setting voltage of the sub-supply line at voltage of the main supply line in the active cycle is provided as a coupling circuit for short-circuiting the supply lines. Accordingly, the voltage drop generated when the supply lines are short-circuited can be prevented. In addition, the processing speed of the logic circuit can be improved.
In particular, diode-connected transistors are placed between supply lines. Then the potential difference between the main supply line and the sub-supply line can be restricted below a fixed value.
In particular, control timing of the voltage of the supply line in the hierarchical power supply system is changed according to an operation mode. Accordingly, current consumption of an internal circuit which operates immediately after activation of the chip and an internal circuit which thereafter operates can be decreased independently.
In particular, the voltage of the supply line in the hierarchical power supply system can be controlled according to an operation mode. The potential of the main supply line and the sub-supply line can thus be controlled according to an operation mode.
In particular, the leakage current in the hierarchical power supply system can be monitored according to a test mode.
The leakage current flowing through the switching transistor of the hierarchical power supply system in the standby cycle can be reduced by applying negative bias to the gate electrode of the switching transistor in the standby cycle. Further, bias control with at least three values prevents raise of substrate voltage occurring with charging/discharging of the gate electrode of the switching transistor, resulting in increase in operable range of the memory cell.
A semiconductor integrated circuit device according to another aspect of the present invention includes a main supply line, a sub-supply line, a coupling circuit for electrically coupling the main supply line and the sub-supply line in an active cycle and electrically uncoupling the main supply line and the sub-supply line in a standby cycle, a logic circuit having a first logic gate operating with voltage on the main supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and having a second logic gate operating with voltage on the sub-supply line as an operation supply voltage, applying a prescribed logical processing based on a supplied input and outputting a resultant one, and a monitor circuit for monitoring the leakage current in the logic circuit.
A principal advantage of the above aspect of the present invention is accordingly that the leakage current in the hierarchical power supply system can be externally monitored.
A semiconductor integrated circuit device according to still another aspect of the present invention includes a semiconductor substrate having a main surface, a main supply line and a sub-supply line extending separately on the main surface of the semiconductor substrate, a coupling circuit electrically coupling the main supply line and the sub-supply line in an active cycle and electrically uncoupling the main supply line and the sub-supply line in a standby cycle, a logic circuit having a first logic gate operating with voltage of the main supply line as an operation supply voltage and applying a prescribed logical processing based on a supplied input to output a resultant one, and having a second logic gate operating with voltage of the sub-supply line as an operation supply voltage and applying a prescribed logical processing based on a supplied input to output a resultant one, a first impurity region formed in the semiconductor substrate to be electrically connected to a portion of at least one of the main supply line and the sub-supply line extending between the coupling circuit and the logic circuit, and a second impurity region formed in the semiconductor substrate to form pn junction between the first impurity region and itself.
A principal advantage in the above aspect of the invention is that a junction capacitance can be produced by the pn junction formed by the first and second impurity regions. The potential of at least one of the main and sub-supply lines can thus be fixed to reduce drop in the power supply occurring with the circuit operation. The drop in the power supply can further be reduced by arranging a number of such junction capacitances at different places. An active region of the logic gate portion is surely formed by arranging the first impurity region next to the region where the first and second logic gates are formed.
The first and second impurity regions are constructed to form the junction capacitance. Accordingly, potential of at least one of the main and sub-supply lines can be fixed, resulting in reduction in the drop of the power supply occurring with the circuit operation.
The junction capacitance refers to the one between potentials of the same value and with different phases. The potential can be fixed more effectively by fixing both ends of the junction capacitance with the same potentials having different noise phases.
The junction capacitance refers to the one between the impurity region electrically connected to the main supply line and the impurity region electrically connected to the sub-supply line. The potential can be fixed more effectively since the potentials of the main and sub-supply lines can be fixed by the junction capacitance.
The junction capacitance refers to the one between an impurity region receiving Vcc potential and an impurity region receiving Vss potential. The Vcc potential and the Vss potential can be fixed by the junction capacitance and the potential can be more effectively fixed accordingly.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.